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Integrated Device Technology, Inc.
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
IDT74FCT16601AT/CT/ET IDT74FCT162601AT/CT/ET PRODUCT PREVIEW
bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg* Common features: istered bus transceivers combine D-type latches and D-type - 0.5 MICRON CMOS Technology flip-flops to allow data flow in either direction in a transparent, - High-speed, low-power CMOS replacement for latched or clocked mode. Each direction has an independent ABT functions latch enable, an independent clock with a clock enable, and an - Typical tSK(o) (Output Skew) < 250ps independent output enable. The package is organized with a - Low input and output leakage 1A (max.) flow-through signal pin organization to ease board layout. All - ESD > 2000V per MIL-STD-883, Method 3015; inputs are designed with hysteresis for improved noise mar> 200V using machine model (C = 200pF, R = 0) gin. - Packages include 25 mil pitch SSOP, 19.6 mil pitch This transceiver is ideally suited for high speed memory TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack interfaces which utilize high speed synchronous writes, by - Extended commercial range of -40C to +85C clocking the data into a high speed register. Reads can then - VCC = 5V 10% be performed in a transparent or latched mode utilizing the * Features for FCT16601AT/CT/ET: same transceiver. - High drive outputs (-32mA IOH, 64mA IOL) The FCT16601AT/CT/ET are ideally suited for driving - Power off disable outputs permit "live insertion" high-capacitance loads and low-impedance backplanes. The - Typical VOLP (Output Ground Bounce) < 1.0V at output buffers are designed with power off disable capability VCC = 5V, TA = 25C to allow "live insertion" of boards when used as backplane * Features for FCT162601AT/CT/ET: drivers. - Balanced Output Drivers: 24mA The FCT162601AT/CT/ET have balanced output drive - Reduced system switching noise with current limiting resistors. This offers low ground bounce, - Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall times-reducing VCC = 5V,TA = 25C the need for external series terminating resistors. The FCT162601AT/CT/ET are plug-in replacements for the DESCRIPTION: FCT16601AT/CT/ET and ABT16601 for on-board bus interThe FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA
1 56 55 2 28 30
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A1
CE 1D C1 CLK CE 1D C1 CLK
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B1
3247 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
5.9
DSC-3247/-
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 53 52 51 50 49 48 47 46 45 44 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND -0.5 to VTERM(3) Terminal Voltage with Respect to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V
C
mA
3247 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
14 SO56-1 43 SO56-2 15 SO56-3 42 16 17 18 19 20 21 22 23 24 25 26 27 28 41 40 39 38 37 36 35 34 33 32 31 30 29
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance
NOTE: 1. This parameter is measured at characterization but not tested.
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Conditions VIN = 0V VOUT = 0V
Typ. 3.5 3.5
Max. Unit 6.0 pF 8.0 pF
3247 lnk 04
CLKBA
SSOP/ TSSOP/TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB OEBA
LEAB LEBA CLKAB CLKBA Ax Bx
A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs A to B Clock Enable Input B to A Clock Enable Input
3247 tbl 01
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Description
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CLKENBA
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FUNCTION TABLE(1,4)
CLKENAB
X X X H L
OEAB
H L L L L L L L
Inputs LEAB X H H L L L L L
CLKAB X X X X L H
A X L H X L H X X
Outputs B Z L H B0(2) L H B0(2) B0(3)
3247 drw 02
L L L
CLKENAB CLKENBA
NOTES: 3247 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Min., IIN = -18mA VCC = Max., VO = GND (3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VCC = Max. VO = 2.7V VO = 0.5V
Min. 2.0 -- -- -- -- -- -- --
Typ.(2) --
-- -- -- -- -- -- -- -0.7 -140
Max.
--
Unit V V A
0.8 1 1 1 1 1 1
-1.2 -225 --
A V mA mV A
VCC = Max., VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS FOR FCT16601T
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage
Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. VIN = VIH or VIL
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-- -80 -- --
100 5
500
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Min. -50 2.5 2.4 2.0 -- --
Typ.(2)
--
Max.
-180
Unit mA V V V V
IOH = -3mA IOH = -15mA IOH = -32mA (4)
3.5 3.5 3.0 0.2 --
-- -- -- 0.55
VOL IOFF
Output LOW Voltage Input/Output Power Off Leakage
VCC = Min. IOL = 64mA VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V
OUTPUT DRIVE CHARACTERISTICS FOR FCT162601T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second.
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Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -24mA IOL = 24mA
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1
A
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Min. 60 -60 2.4 --
Typ.(2) 115 -115 3.3 0.3
Max. 200 -200 -- 0.55
Unit mA mA V V
3247 lnk 07
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) Min. -- VIN = VCC VIN = GND -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz
OEAB = VCC OEBA =
VCC = Max., Outputs Open GND One Input Toggling 50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEAB = GND CLKENBA = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEAB = GND CLKENBA = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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VIN = 3.4V VIN = GND
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3.8 6.5(5) 8.5 20.8(5)
--
--
3247 tbl 09
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16601AT/ FCT162601AT Symbol Parameter Condition(1) Min.(2) Max. FCT16601CT/ FCT162601CT Min.(2) Max. FCT16601ET/ FCT162601ET Min.(2) Max. Unit
fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tSU tH tW
CLKAB or CLKBA frequency(4)
CL = 50pF
-- 1.5 1.5 1.5 1.5 1.5 4.0 0 1.0 2.5 2.0 2.5 0 2.5
150 4.9 5.2 4.7 5.8 6.2 -- -- -- -- --
-- 1.5 1.5 1.5 1.5 1.5 3.0 0
150 4.4 4.7 4.5 5.3 5.7
-- 1.5 1.5 1.5 1.5 1.5 2.4 0 1.0 1.5 0.5 2.0 0 2.5 3.0 --
150 3.8 4.2 4.2 4.8 5.2 -- -- -- -- -- -- -- -- -- 0.5
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3247 tbl 09
Propagation Delay RL = 500 Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax after CLKAB, Bx after CLKBA Set-up Time HIGH or LOW Clock LOW Ax to LEAB, Bx to LEBA Clock HIGH Hold Time, HIGH or LOW Ax after LEAB, Bx after LEBA Set-up Time, CLKEN to CLK Hold Time, CKLEN after CLK
LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3)
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-- -- -- --
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1.0 2.0 1.5 2.5 0 2.5 3.0 --
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--
W
--
-- -- -- -- -- -- -- 0.5
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
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3.0 --
0.5
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
3247 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
3247 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE
tREM
tSU
tH
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HIGH-LOW-HIGH PULSE
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1.5V tW 1.5V
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PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
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tPHL
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ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
3247 drw 08
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
tPHL
VOL
3247 drw 07
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
X Temperature Range
FCT XXXX X Device Type Package
PV PA PF
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3)
16601AT Non-Inverting 18-Bit Registered Transceiver 16601CT 16601ET 162601AT 162601CT 162601ET 74 -40C to +85C
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